Multi-Rate Discrete Domain Modeling of Power Hardware-in-The-Loop Setups

被引:4
作者
Ashrafidehkordi, Fargah [1 ]
Kottonau, Dustin [1 ]
De Carne, Giovanni [1 ]
机构
[1] Karlsruhe Inst Technol, Inst Tech Phys, D-76344 Karlsruhe, Germany
来源
IEEE OPEN JOURNAL OF POWER ELECTRONICS | 2023年 / 4卷
关键词
Power Hardware In the Loop; digital real-time simulations; power hardware in the loop stability; multi-rate discrete-time sampling; STABILITY ANALYSIS; IMPROVED ACCURACY; SIMULATION; INTERFACE; SYSTEMS; DESIGN;
D O I
10.1109/OJPEL.2023.3283035
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Power Hardware-in-the-Loop (PHIL) facilitates the testing of novel power engineering solutions in the lab, allowing a flexible testing environment while keeping the high testing fidelity of real hardware. Due to the analog/digital intersection of the PHIL setup, selecting simply continuous or single-rate discrete-time domain fails to model such a hybrid system accurately. This article proposes a multi-rate discrete-time modeling approach of a PHIL setup that can estimate the mixed analog and digital nature of the PHIL accurately, resulting in accuracy improvement over a wide range of frequencies. The proposed approach applies two different sampling times, a large one connected to the digital simulator and a small one for modeling the analog-hardware part. Dynamics and delays of interfaces, such as analog-to-digital converters, the power amplifier, the sensor, and the low-pass filter, have been accurately modeled and validated by means of experimental results.
引用
收藏
页码:539 / 548
页数:10
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