A Low Power Digitizer with Piecewise-Linear Counting Technique for High Dynamic Range Nonacell-Based 3-D-Stacked CMOS Image Sensor

This paper describes a low power digitizer for 3D-stacked high dynamic range (HDR) CMOS image sensors (CIS). It digitizes the electrical output signals from the pixel array on the upper chip in the 3-D-stacked CIS. It consists of a single-slope analog-to-digital converters (ADC) array with a comparator array and a digital counter array. To improve the power-efficiency of the HDR image generation systems, a piecewise-linear counting technique for an intra-scene dual-conversion gain (i-DCG) methodology is proposed. To optimize the power consumption of the ADC array, a decision-feedback technique and a hybrid counter structure are utilized in the comparator array and the counter array, respectively. With the proposed digitizer architecture, the ADC consumes only 22.8 mu W/column, which is remarkably power-efficient. Implemented in a 28 nm process technology, the proof-of-concept prototype achieves a random noise (RN) of 89 mu V, a column fixed-pattern noise (FPN) of 6.5 ppm, and an integrated nonlinearity (INL) of 2 ppm at the analog gain of 16.