Towards Quantized Stochastic Computing by Leveraging Reduced Precision Binary Numbers through Bit Truncation

Stochastic computing (SC) offers high hardware efficiency and error tolerance but faces challenges, such as the overhead of converting between binary and stochastic forms. This paper introduces a novel quantized SC architecture, significantly reducing stochastic number generator (SNG) hardware complexity. We achieve this by quantizing binary numbers to lower precision using various bit truncation schemes, thereby reducing SNG overhead. Implemented in a 65-nm CMOS process, our proposed quantized SNG reduces area and power by up to 65.5% and 73.0%, respectively, compared to the conventional full-precision SNG. We also demonstrate that our SC schemes have minimal impact on processing quality while greatly improving hardware efficiency, as seen in a digital image processing application.