Extracting edge conduction around threshold in mesa-isolated SOI MOSFETs

被引：1

作者：

Boutayeb, A. ^{[1
,2
,3
]}

Theodorou, C. ^{[3
]}

Golanski, D. ^{[1
]}

Batude, P. ^{[2
]}

Brunet, L. ^{[2
]}

Bosch, D. ^{[2
]}

Guyader, F. ^{[1
]}

Joblot, S. ^{[1
]}

Ponthenier, F. ^{[2
]}

Lacord, J. ^{[2
]}

机构：

[1] STMicroelect Crolles, Grenoble, France

[2] Univ Grenoble Alpes, CEA Leti, F-38000 Grenoble, France

[3] Univ Grenoble Alpes, Univ Savoie Mt Blanc, CNRS, Grenoble INP,IMEP LAHC, F-38000 Grenoble, France

来源：

SOLID-STATE ELECTRONICS | 2023年 / 209卷

关键词：

Mesa isolation; SOI transistor; TCAD; Parasitic transistor; Decomposing methodology; Edge contribution; Planar transistor; VOLTAGE;

D O I：

10.1016/j.sse.2023.108736

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work proposes a methodology to decompose the center and edge current contributions around threshold in mesa-isolated SOI MOSFETs using 3D TCAD simulations. Applied to pMOS measurements, it reveals that the subthreshold regime is driven by the active edge, whatever the device width. It also explains why the threshold voltage modulation by the back-gate bias depends on the device width, as well as why these effects are worse for high channel doping values.

引用

页数：6

共 15 条

[1] MEASUREMENT AND MODELING OF THE SIDEWALL THRESHOLD VOLTAGE OF MESA-ISOLATED SOI MOSFETS
MATLOUBIAN, M
SUNDARESAN, R
LU, H
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1989, 36 (05) : 938 - 942
[2] MODELING OF EDGE THRESHOLD VOLTAGE OF MESA-ISOLATED N-CHANNEL MOSFETS ON FULLY-DEPLETED THIN-FILM SOI
PARK, JW
HAN, CH
KIM, CK
SOLID-STATE ELECTRONICS, 1994, 37 (07) : 1449 - 1452
[3] Measurement and modeling of the sidewall threshold voltage of mesa-isolated SOI MOSFET's
Matloubian, Mishel, 1600, (36):
[4] Investigation of anomalous leakage current in mesa-isolated SOI MOSFET's
Iwamatsu, T
Yamaguchi, Y
Ipposhi, T
Maegawa, S
Inoue, Y
Nishimura, T
IEEE ELECTRON DEVICE LETTERS, 1997, 18 (10) : 499 - 502
[5] Investigation of anomalous leakage current in mesa-isolated SOI MOSFET's
Mitsubishi Electric Corp, Hyogo, Japan
IEEE Electron Device Lett, 10 (499-502):
[6] Theoretical analysis of edge parasitic transistor effects in mesa-isolated fully-depleted SOI NMOS devices
Wang, HM
Xi, XM
Zhang, X
Wang, YY
INTERNATIONAL JOURNAL OF ELECTRONICS, 1998, 85 (01) : 11 - 19
[7] Threshold voltage model for mesa-isolated small geometry fully depleted SOI MOSFETs based on analytical solution of 3-D Poisson's equation
Katti, G
DasGupta, N
DasGupta, A
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (07) : 1169 - 1177
[8] Hot carrier induced degradation in mesa-isolated n-channel SOI MOSFETs operating in a Bi-MOS mode
Huang, R
Wang, JY
Zhang, X
Wang, YY
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (08) : 1594 - 1598
[9] Degradation characteristics of STI and MESA-isolated thin-film SOI CMOS
Huang, CL
Grula, GJ
IEEE ELECTRON DEVICE LETTERS, 1997, 18 (10) : 474 - 476
[10] An Analytical Model for Deriving the 3-D Potentials and the Front and Back Gate Threshold Voltages of a Mesa-Isolated Small Geometry Fully Depleted SOI MOSFET
Lee, Jae Bin
Suh, Chung Ha
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2012, 12 (04) : 473 - 481

← 1 2 →