共 12 条
[1]
Bingshou Xiong, 2011, 2011 IEEE 13th Electronics Packaging Technology Conference (EPTC 2011), P138, DOI 10.1109/EPTC.2011.6184402
[2]
Stress Analysis and Design Optimization for Low-k Chip With Cu Pillar Interconnection
[J].
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY,
2015, 5 (09)
:1273-1283
[3]
Chen Xuanlong, 2017, 2017 IEEE 24 INT S P
[4]
Fine Pitch Cu Pillar with Bond on Lead (BOL) Assembly Challenges for Low Cost and High Performance Flip Chip Package
[J].
2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017),
2017,
:102-107
[5]
The mechanism of dense interfacial voids and its impact on solder joint reliability
[J].
2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC),
2016,
:1128-1134
[6]
Ostrowicki GT, 2015, ELEC COMP C, P127, DOI 10.1109/ECTC.2015.7159581
[7]
Serebreni M., 2018, 2018 19 INT C THERMA, P1
[8]
Stoyanov S, 2013, INT SPR SEM ELECT TE, P253, DOI 10.1109/ISSE.2013.6648252
[9]
Sun W, 2008, 2008 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING, VOLS 1 AND 2, P671
[10]
Challenges of Large Body FCBGA on Board Level Assembly and Reliability
[J].
2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018),
2018,
:1962-1967