共 50 条
[45]
Power-rail ESD Clamp Circuit with Hybrid-detection Enhanced Triggering in a 65-nm, 1.2-V CMOS Process
[J].
2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS),
2017,
:589-592
[46]
Resistor-Less Power-Rail ESD Clamp Circuit with Ultra-Low Leakage Current in 65nm CMOS Process
[J].
2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS),
2013,