New Power Clamp Circuit for Concurrent ESD and Surge Protections

被引:5
作者
Yang, Zhaonian [1 ]
Xu, Jinghao [1 ]
Fu, Dongbing [2 ]
Zhang, Yan [1 ,3 ]
Zhang, Yue
Yang, Yuan [1 ]
Yu, Ningmei [1 ]
机构
[1] Xian Univ Technol, Shaanxi Key Lab Complex Syst Control & Intelligent, Xian 710048, Peoples R China
[2] Chongqing Gigachip Technol Co Ltd, Chongqing 401332, Peoples R China
[3] Xidian Univ, Sch Telecommun Engn, Xian 710071, Peoples R China
基金
中国国家自然科学基金;
关键词
Clamp circuit; diode string; electrostatic discharge (ESD); leakage current; surge; trigger voltage;
D O I
10.1109/TED.2023.3296071
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An important development trend of ON-chip power clamp circuits is that they should be able to deal with more types of power rail overstress events, such as electrostatic discharges (ESDs) and surges. Generally, this requires that the clamp circuit can be fully turned on for the whole duration of the overstress events. In this work, a new MOSFET-based power clamp circuit for concurrent ESD and surge protection is proposed and successfully validated experimentally. An MOSFET controlled by a special bias circuit is inserted into a traditional voltage detector consisting of a diode string and a resistor, resulting in reductions in the leakage current and the trigger voltage. Moreover, the layout area of the proposed clamp circuit is smaller than the traditional RC-and diode-triggered clamp circuits. Practical application scenarios and performance comparisons with traditional circuits are also presented.
引用
收藏
页码:4538 / 4546
页数:9
相关论文
共 50 条
[41]   The Failure Mechanism of Internal Circuit During ESD Striking a Power to Another Power [J].
Liao, Chih-Cherng ;
Li, Ching-Ho ;
Nidhi, Karuna ;
Chuang, Chieh-Yao ;
Liao, Hsien-Feng ;
Jou, Yeh-Ning ;
Chen, Ke-Horng ;
Lee, Jian-Hsing .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2024, 24 (04) :472-479
[42]   ESD characterization of a 190V LIGBT SOI ESD power clamp structure for plasma display panel applications [J].
Jiang, Lingli ;
Fan, Hang ;
Qiao, Ming ;
Zhang, Bo ;
Li, Zhaoji .
MICROELECTRONICS RELIABILITY, 2013, 53 (05) :687-693
[43]   Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process [J].
Ker, MD ;
Lo, WY .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (04) :601-611
[44]   High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process [J].
Ker, Ming-Dou ;
Lin, Chun-Yu .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (07) :1636-1641
[45]   Power-rail ESD Clamp Circuit with Hybrid-detection Enhanced Triggering in a 65-nm, 1.2-V CMOS Process [J].
Lu, Guangyi ;
Wang, Yuan ;
Wang, Yize ;
Zhang, Xing .
2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017, :589-592
[46]   Resistor-Less Power-Rail ESD Clamp Circuit with Ultra-Low Leakage Current in 65nm CMOS Process [J].
Yeh, Chih-Ting ;
Ker, Ming-Dou .
2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2013,
[47]   Design of GaN-on-Silicon Power-Rail ESD Clamp Circuit With Ultralow Leakage Current and Dynamic Timing-Voltage Detection Function [J].
Ke, Chao-Yang ;
Ker, Ming-Dou .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2025, 72 (03) :1066-1074
[48]   Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors [J].
Huang, Yi-Chun ;
Ker, Ming-Dou .
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2023, 11 :84-94
[49]   New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology [J].
Yeh, Chih-Ting ;
Ker, Ming-Dou .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2012, 59 (03) :178-182
[50]   Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology [J].
Wang, Chang-Tzu ;
Ker, Ming-Dou .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (06) :1460-1465