New Power Clamp Circuit for Concurrent ESD and Surge Protections

An important development trend of ON-chip power clamp circuits is that they should be able to deal with more types of power rail overstress events, such as electrostatic discharges (ESDs) and surges. Generally, this requires that the clamp circuit can be fully turned on for the whole duration of the overstress events. In this work, a new MOSFET-based power clamp circuit for concurrent ESD and surge protection is proposed and successfully validated experimentally. An MOSFET controlled by a special bias circuit is inserted into a traditional voltage detector consisting of a diode string and a resistor, resulting in reductions in the leakage current and the trigger voltage. Moreover, the layout area of the proposed clamp circuit is smaller than the traditional RC-and diode-triggered clamp circuits. Practical application scenarios and performance comparisons with traditional circuits are also presented.