Comparing FPGA-Based Adders and Application to the Implementation of a Digital FIR Filter

被引：0

作者：

Woelfle, Justin ^{[1
]}

Chabini, Noureddine ^{[2
]}

Beguenane, Rachid ^{[2
]}

机构：

[1] Queens Univ, Dept Elect & Comp Engn, Kingston, ON, Canada

[2] Royal Mil Coll Canada, Dept Elect & Comp Engn, Kingston, ON, Canada

来源：

2023 IEEE CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, CCECE | 2023年

关键词：

FPGA; adder; multiplier; FIR filter;

D O I：

10.1109/CCECE58730.2023.10288654

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

Field Programmable Gate Arrays (FPGAs) are being used in the realization of real-life applications. Adders are required in data processing units and in the realization of other arithmetic operators. We compare three types of FPGA-based adders, propose optimizations, and use the non-optimized and optimized adders for realizing a digital Finite Impulse Response (FIR) filter on FPGA and we compare the implementations. As an FPGA platform, we used the Altera Cyclone IV. The used synthesis tool is the Quartus Prime 19.1 from Altera. Experimental results are provided and discussed.

引用

页数：4

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