A Parallel Implementation of 3D Graphics Pipeline

Graphics pipelines include many custom accelerators which are difficult to design and not readily scalable. A graphics rendering pipeline mainly includes a front-end processor (FEP), a primitive assembler, a vertex shader stage (performing model view transform, vertex coloring, projection transform), back-face culling, 3D clipping, window transform, rasterizer, pixel shading, and fragment operations. These accelerators determine the performance of rendering. The main operation of the rasterization stage is to convert primitives into pixels. Rendering without accelerators is also viable if the SIMT (Single-Instruction Multiple-Thread) engines on a modern GPU (Graphics Processing Unit) are well-utilized. Compared with the standard TBR algorithm, this paper improves the original serial algorithm into a parallel algorithm to improve the rendering performance. A highly parallel implementation in this approach, from the very first stage of primitive assembly to fragment operations, boosts performance as experimental results indicate.