A Novel Ultra-Low Voltage Fully Synthesizable Comparator exploiting NAND Gates

被引：5

作者：

Della Sala, Riccardo ^{[1
]}

Bocciarelli, Cristian ^{[1
]}

Centurelli, Francesco ^{[1
]}

Spinogatti, Valerio ^{[1
]}

Trifiletti, Alessandro ^{[1
]}

机构：

[1] Sapienza Univ Rome, Via Eudossiana 18, I-00184 Rome, Italy

来源：

2023 18TH CONFERENCE ON PH.D RESEARCH IN MICROELECTRONICS AND ELECTRONICS, PRIME | 2023年

关键词：

Dynamic comparator; fully-synthesizable; standard cell-based; ultra-low voltage; ultra-low power; Internet of Things;

D O I：

10.1109/PRIME58259.2023.10161936

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work a novel ultra-low voltage, ultra-low power fully synthesizable comparator is presented. The proposed architecture exploits only 2-input NAND gates, that allow minimization of the area footprint and scalability up to extremely low supply voltages. An extensive simulation campaign in a 130 nm CMOS technology has shown state-of-the-art performance in terms of power-delay-product for supply voltages down to 0.3V. Simulations also show good robustness under mismatch and PVT variations, proving the feasibility of the approach.

引用

页码：21 / 24

页数：4

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