A Low-Voltage Submicrowatt, High-Speed CMOS Dynamic Comparator

被引：0

作者：

Shakibaee, Fatemeh ^{[1
]}

Gosselin, Benoit ^{[1
]}

机构：

[1] Laval Univ, Dept Elect & Comp Engn, Quebec City, PQ, Canada

来源：

2023 21ST IEEE INTERREGIONAL NEWCAS CONFERENCE, NEWCAS | 2023年

关键词：

double-tail latch-type comparator; dynamic comparator; high speed; power-efficient; Strong-Arm comparator; ADC;

D O I：

10.1109/NEWCAS57931.2023.10198089

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present an energy-efficient dynamic comparator that is suitable for low-voltage and high-speed applications. The preamplifier circuit prevents fully discharging the output nodes without utilizing an extra capacitor, which improves power consumption and operating speed compared to other solutions. The comparator is designed in a 65-nm CMOS technology at a power supply of 1.2 V. The designed comparator operates at a frequency of 1.2 MHz, consumes 931.1 nW, and has a delay of 0.64 ns at Delta V-in = 1 mV. To estimate the offset of the proposed circuit, Monte Carlo simulations were performed and resulted in a standard deviation of 1.54 mV and a mean of 1.06 mV.

引用

页数：5

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