A 0-to-35mA NMOS Capacitor-Less LDO with Dual-Loop Regulation Achieving 3ns Response Time and 1pF-to-10nF Loading Range

被引：3

作者：

Hsu, Wen-Yang ^{[1
]}

Aymerich, Joan ^{[1
]}

Yang, Xiaolin ^{[1
]}

Sawigun, Chutham ^{[1
]}

Coppejans, Philippe ^{[1
]}

Lopez, Carolina Mora ^{[1
]}

机构：

[1] Imec, Leuven, Belgium

来源：

IEEE 49TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE, ESSCIRC 2023 | 2023年

关键词：

low-dropout regulator; LDO; VCO-based LDO; time-based LDO; fast transient response; CP;

D O I：

10.1109/ESSCIRC59616.2023.10268699

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a capacitor-less low-dropout voltage regulator (LDO) based on an NMOS pass transistor and a dual-loop regulation. The first capacitively-coupled loop responds to a fast change of load currents, whereas the second time-based loop provides a high-precision regulation without requiring an external clock. Our proposed LDO, implemented in a 55nm CMOS, achieves a 3ns response time and a 240mV undershoot voltage when a large transient load step of 0-35mA and 2ns edge time is applied. Moreover, our design is stable over a wide range of capacitive (1pF to 10nF) and current loads (0 to 35mA) while consuming 16 similar to 35 mu A and an active chip area is 0.097mm(2).

引用

页码：253 / 256

页数：4

共 11 条

[1] A CMOS bandgap reference circuit with sub-1-V operation [J].