Efficient Design of FGMOS-Based Low-Power Low-Voltage XOR Gate

Full adders (FAs) are the core elements and substantially impact the performance of digital signal processing applications such as arithmetic logic unit (ALU). In this paper, XOR gate-based FA design is presented that can operate appropriately in the domain of ultra-low voltage (LV) and low power (LP). In this treatise, FGMOS technique is used to elevate the performance in terms of design complexity and to reduce the power requirements. Important device performance characteristics such as power (pwr), delay (tp), power delay product (PDP) and energy delay product (EDP) are explored for the proposed FGMOS XOR gate design, and existing XOR designs are used to assess the results. This research paper presents a low-power FGMOS XOR gate design with a total power consumption of 5.39 pW at 0.7 V supply. Further, in this work, 1-bit FGMOS-based ALU is proposed to perform the functions of full adder, NAND, NOR and XOR. To ameliorate the performance of the circuit, FGMOS-based NAND and NOR gate designs are also proposed in this treatise. Aforementioned full adder and XOR gate along with pass-transistor logic (PTL)-based multiplexers are used to design efficient design of 1-bit ALU at 22-nm technology node. This research paper explicates the utility of FGMOS technique for the designing of high-performance complex digital circuits.