The Case for Performance Interfaces for Hardware Accelerators

被引:2
作者
Iyer, Rishabh [1 ]
Ma, Jiacheng [1 ]
Argyraki, Katerina [1 ]
Candea, George [1 ]
Ratnasamy, Sylvia [2 ]
机构
[1] Ecole Polytech Fed Lausanne, Lausanne, Switzerland
[2] Univ Calif Berkeley, Berkeley, CA USA
来源
PROCEEDINGS OF THE 19TH WORKSHOP ON HOT TOPICS IN OPERATING SYSTEMS, HOTOS 2023 | 2023年
关键词
D O I
10.1145/3593856.3595904
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
While systems designers are increasingly turning to hardware accelerators for performance gains, realizing these gains is painstaking and error-prone. It can take several person-months to determine if a given accelerator is a good fit for a given piece of code, and accelerators that cost millions of dollars to build can slow down the very systems they were designed to accelerate. We argue that hardware accelerators must come with performance interfaces-interfaces that provide usable information about the accelerator's performance behavior just like semantic interfaces do for functionality-to facilitate their correct use. Since accelerators do not provide new functionality and are only useful if they improve system performance, performance interfaces are as integral to their correct use as semantic interfaces.
引用
收藏
页码:38 / 45
页数:8
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