A 13-bit 70MS/s SAR-Assisted 2-bit/cycle Cyclic ADC with Offset Cancellation and Slack-Borrowing Logic

被引：1

作者：

Jiang, Rucheng ^{[1
]}

Wu, Han ^{[1
]}

Ng, Kian Ann ^{[2
]}

Tsai, Chne-Wuen ^{[1
]}

Yoo, Jerald ^{[1
,3
]}

机构：

[1] Natl Univ Singapore, Dept Elect & Comp Engn, Singapore, Singapore

[2] Digipen Inst Technol, Singapore, Singapore

[3] N1 Inst Hlth, Singapore, Singapore

来源：

IEEE 49TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE, ESSCIRC 2023 | 2023年

关键词：

2-bit/cycle Cyclic ADC; offset cancellation; slack borrowing; SAR-assisted Cyclic ADC;

D O I：

10.1109/ESSCIRC59616.2023.10268690

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an energy and area-efficient successive approximation register (SAR)-assisted cyclic analog-to-digital converter (ADC) architecture. The proposed hybrid ADC combines a 2-bit/cycle cyclic ADC with a slack-borrowing coarse SAR ADC. The proposed multiply-by-one cyclic ADC achieves low-power and 2-bit/cycle operation without any extra hardware cost. The simultaneous amplifier and comparator offset cancellation mitigates the 2nd-stage cyclic ADC offset. Clocked at 70MS/s, the proposed ADC consumes 0.88mW, yielding FoMS and FoMW of 175dB and 6.9fJ/conv, respectively.

引用

页码：281 / 284

页数：4