Impedance Characterization of a Return-to-Zero (RZ) Current Steering Digital-to-Analog Converters

被引：1

作者：

Naguib, Ahmed ^{[1
]}

机构：

[1] Mil Tech Coll, Dept Elect Engn, Integrated Circuits & Syst Grp, Mixed & RFIC Lab, Cairo, Egypt

来源：

SOUTHEASTCON 2023 | 2023年

关键词：

Return to zero; current steering DAC; high-speed; linearity; spurious free dynamic range (SFDR);

D O I：

10.1109/SoutheastCon51012.2023.10115094

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper introduces an impedance characterization for a high-speed return to zero (RZ) current steering digital to analog converter (CSDAC). It shows the effect of the cell impedance variation on the RZ-CSDAC dynamic performance. Targeting Gigahertz sampling speed, a degradation of RZ-CSDAC output impedance is presented. Consequently, it represents a limiting factor in achieving high linearity with increasing the sampling frequency. The RZ-CSDAC unit cell is designed and simulated in 45nm SOI CMOS technology.

引用

页码：706 / 707

页数：2

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