On the Zero Temperature Coefficient in Cryogenic FD-SOI MOSFETs

被引：10

作者：

Catapano, E. ^{[1
,2
]}

Frutuoso, T. Mota ^{[2
]}

Casse, M. ^{[2
]}

Ghibaudo, G. ^{[1
]}

机构：

[1] Univ Grenoble Alpes, Minatec, IMEP LAHC, F-38016 Grenoble, France

[2] Univ Grenoble Alpes, Minatec, CEA LETI, F-38054 Grenoble, France

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2023年 / 70卷 / 03期

基金：

欧洲研究理事会;

关键词：

Capacitance; Logic gates; Silicon; Scattering; MOSFET; Temperature; Phonons; Cryogenic electronics; FDSOI; modeling; zero temperature coefficient (ZTC); POINT;

D O I：

10.1109/TED.2022.3215097

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this article, we propose an explanation of the origin of the zero-temperature coefficient (ZTC) in fully depleted-silicon on insulator (FD-SOI) MOSFETs capacitance curves from room to cryogenic temperature. It is demonstrated that the ZTC is a natural consequence of the Fermi-Dirac function controlling the carrier population. Moreover, based on transport analysis in linear region, it is proven that the ZTC point is preserved in the drain current transfer characteristics only if the mobility varies as the reciprocal temperature, i.e., if it is purely phonon scattering-limited. The inclusion of other defective scattering mechanisms dispels the ZTC point. Finally, the model developed is validated by some TCAD simulations down to deep cryogenic temperatures.

引用

页码：845 / 849

页数：5

共 13 条

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