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- [1] Modeling Techniques for Board Level Drop Test for a Wafer-Level Package 2008 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING, VOLS 1 AND 2, 2008, : 994 - +
- [2] Electrical Modeling and Design of a Wafer-Level Package for MEM Resonators IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2010, 33 (02): : 534 - 542
- [6] Inductors from Wafer-Level Package Process for High Performance RF Applications 2009 11TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2009), 2009, : 899 - +
- [7] Radiated EMI Prediction and Mechanism Modeling from Measured Noise of Microcontroller 2010 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY & TECHNICAL EXHIBITION ON EMC RF/MICROWAVE MEASUREMENTS & INSTRUMENTATION, 2010, : 727 - 730
- [8] IC Laser Trimming Speed-Up through Wafer-Level Spatial Correlation Modeling 2014 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2014,
- [10] Physics-based Nested-ANA Approach for Fan-Out Wafer-Level Package Reliability Prediction IEEE 72ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2022), 2022, : 1827 - 1833