Overlay challenges in the era of High-NA

High-NA EUV lithography represents the next chapter in advancing Moore's Law. The relentless march toward progressively tighter geometries drives a reliance on pitch-division and multi-patterning techniques such as SADP, SAQP, SALELE, and others to overcome lithographic resolution limitations. Unfortunately, these approaches come with a cost in the form of extra lithography steps and increased process complexity. In technology nodes that are heavily dependent on pitch-division and multi-patterning, overlay control becomes extremely challenging, as tighter budgets are required to compensate for the additional sources of edge placement error and control of a current layer reticle to multiple underlayers is required. In recent years, the improved resolution of Low-NA EUV has helped to replace 193 nm immersion-based pitch division schemes with direct print, greatly reducing process complexity and thus providing a degree of respite for overlay control. However, as patterning requirements continue to tighten in accordance with Moore's Law, even the Low-NA EUV becomes insufficient for direct patterning of the required geometries, forcing a return to pitch division. Intel intends to avoid Low-NA EUV + pitch division and move aggressively to High-NA EUV lithography for production in 2025. Unlike previous generation lithography platforms, High-NA EUV does create some additional challenges for overlay control and this talk will be focused on addressing those items.