Extreamly Advanced Cu Interconnect with Selective ALD Barrier for High Performance Logic Device

被引：2

作者：

Jang, Junki ^{[1
]}

Park, Kyoungpil ^{[1
]}

Park, Chibeom ^{[1
]}

Yoo, Seungyong ^{[1
]}

Cha, Seungkeun ^{[1
]}

Nam, Kyounghee ^{[1
]}

Kim, Kihyun ^{[1
]}

Son, Jeongwook ^{[1
]}

Park, Eunyoung ^{[1
]}

Lee, Jaeho ^{[1
]}

Kim, Joosung ^{[1
]}

Lee, Miji ^{[1
]}

Yeo, Myungsoo ^{[1
]}

Jung, Eunji ^{[1
]}

Kim, Rak-hwan ^{[1
]}

Park, Doohwan ^{[1
]}

Kim, Chin ^{[1
]}

Choi, Yunki ^{[1
]}

Ha, Taehong ^{[1
]}

Ahn, Jeonghoon ^{[1
]}

Ku, Jahum ^{[1
]}

机构：

[1] Samsung Elect Inc, Foundry Business, Hwasung, Gyeonggi, South Korea

来源：

2023 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, IITC AND IEEE MATERIALS FOR ADVANCED METALLIZATION CONFERENCE, MAM, IITC/MAM | 2023年

关键词：

Cu; Barrierless; ALD TaN; TAN;

D O I：

10.1109/IITC/MAM57687.2023.10154689

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

In this paper, selective atomic layer deposition (ALD) TaN barrier process was described for advanced high performance logic device. Compared to conventional ALD deposited barrier, selective barrier adopted process showed 40% lower via resistance and comparable electrical healthiness at various via test structures. By applying this process, we achieved better chip performance and comparable chip yield using internal foundry product. This result demonstrates manufacturability of a selective barrier for advanced high performance logic device.

引用

页数：3

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