SPCTRE: sparsity-constrained fully-digital reservoir computing architecture on FPGA

被引：0

作者：

Abe, Yuki ^{[1
,4
]}

Nishida, Kohei ^{[2
]}

Ando, Kota ^{[3
]}

Asai, Tetsuya ^{[3
]}

机构：

[1] Hokkaido Univ, Grad Sch Informat Sci & Technol, Sapporo, Japan

[2] Hokkaido Univ, Fac Engn, Sapporo, Hokkaido, Japan

[3] Hokkaido Univ, Fac Informat Sci & Technol, Sapporo, Japan

[4] Hokkaido Univ, Fac Informat Sci & Technol, Grad Sch, Kita 14,Nishi 9,Kita Ku, Sapporo 0600814, Japan

来源：

INTERNATIONAL JOURNAL OF PARALLEL EMERGENT AND DISTRIBUTED SYSTEMS | 2024年 / 39卷 / 02期

关键词：

Reservoir computing; parallel computing architecture; FPGA implementation; NETWORK;

D O I：

10.1080/17445760.2024.2310576

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper proposes an unconventional architecture and algorithm for implementing reservoir computing on FPGA. An architecture-oriented algorithm with improved throughput and architecture designed to reduce memory and hardware resource requirements are presented. The proposed architecture exhibits good performance in terms of benchmarks for reservoir computing. A prediction accelerator for reservoir computing that operates on 55.45 mW at 450 K fps with <3000 LEs is realized by implementing the architecture on FPGA. The proposed approach presents a novel FPGA implementation of reservoir computing focussing on both algorithms and architecture that may serve as a basis for applications of AI at network edge. [GRAPHICS] .

引用

页码：197 / 213

页数：17