Variations of single event transient induced by line edge roughness (LER) and temperature in FinFET

The impacts of line edge roughness (LER) and temperature effect on single event transient (SET) in Silicon-On -Insulator (SOI) FinFET at 14 nm technology node are studied. Based on the calibrated model of the rectangle FinFET, all of possible fin structures induced by LER in the vertical direction are proposed by considering the correlation between the line edges. When an energetic particle hits, due to the corporate effects of the gate control capability from the equivalent gate width and the current density from the cross section, thin fin shape represents more immunity to SET with the relative decrement in current peak, collected charge, deposited charge, pulse width and bipolar amplification coefficient by 23.78 %, 31.61 %, 19.16 %, 23.77 % and 15.40 %, respectively. However, the SET responses of big bottom and fat fin structures indicate that they are more sen-sitive to SET. Because of the driven current increase induced by the inversion of the temperature effect in FinFET, as the environment temperature increases, the SET responses of all of fin shapes decrease and their relative decrements are close. When the temperature increases from 258K to 398K, the average relative decrements in current peak, and collected charge are 24.22 %, 20.90 %, respectively.