Reinforcement Learning or Simulated Annealing for Analog Placement? A Study based on Bounded-Sliceline Grids

Analog placement is a crucial phase in analog integrated circuit synthesis, impacting the quality and performance of the final circuits. This process involves determining the physical positions of analog building blocks while minimizing chip area and interconnecting wire-length. Existing methodologies often rely on the simulated-annealing (SA) approach, prioritizing constraints like symmetryisland, proximity, and well-island. We present a novel reinforcement learning (RL) based analog placement methodology on the bounded-sliceline grid (BSG) structure. Introducing a hierarchical clustering feature in BSG, we address well-island, proximity, and symmetry constraints. In experimental comparisons with the SA approach, our RL-based method exhibits superior placement quality across various analog circuits.