HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance Scaling

被引:13
作者
Bouzidi, Halima [1 ]
Odema, Mohanad [2 ]
Ouarnoughi, Hamza [1 ]
Al Faruque, Mohammad Abdullah [2 ]
Niar, Smail [1 ]
机构
[1] Univ Polytech Hauts De France, LAMIH UMR CNRS, Valenciennes, France
[2] Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA USA
来源
2023 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE | 2023年
基金
美国国家科学基金会;
关键词
dynamic neural networks; DVFS; neural architecture search; early exit; edge computing; joint optimization;
D O I
10.23919/DATE56975.2023.10137095
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Dynamic neural networks (DyNNs) have become viable techniques to enable intelligence on resource-constrained edge devices while maintaining computational efficiency. In many cases, the implementation of DyNNs can be sub-optimal due to its underlying backbone architecture being developed at the design stage independent of both: (i) potential support for dynamic computing, e.g. early exiting, and (ii) resource efficiency features of the underlying hardware, e.g., dynamic voltage and frequency scaling (DVFS). Addressing this, we present HADAS, a novel Hardware-Aware Dynamic Neural Architecture Search framework that realizes DyNN architectures whose backbone, early exiting features, and DVFS settings have been jointly optimized to maximize performance and resource efficiency. Our experiments using the CIFAR-100 dataset and a diverse set of edge computing platforms have shown that HADAS can elevate dynamic models' energy efficiency by up to 57% for the same level of accuracy scores. Our code is available at https://github.com/HalimaBouzidi/HADAS
引用
收藏
页数:6
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