Real-Time Guarantees in Routerless Networks-on-Chip

被引:0
作者
Indrusiak, Leandro Soares [1 ]
Burns, Alan [1 ]
机构
[1] Univ York, Dept Comp Sci, Deramore Lane, York YO10 5GH, N Yorkshire, England
关键词
Response time analysis; real-time networks; ARCHITECTURE; DESIGN; NOC;
D O I
10.1145/3616539
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This article considers the use of routerless networks-on-chip as an alternative on-chip interconnect for multiprocessor systems requiring hard real-time guarantees for inter-processor communication. It presents a novel analytical framework that can provide latency upper bounds to real-time packet flows sent over routerless networks-on-chip, and it uses that framework to evaluate the ability of such networks to provide real-time guarantees. Extensive comparative analysis is provided, considering different architectures for routerless networks and a state-of-the-art wormhole network based on priority-preemptive routers as a baseline.
引用
收藏
页数:27
相关论文
共 50 条
[41]   Energy Aware Networks-on-Chip Cortex Inspired Communication [J].
Moreac, Erwan ;
Laurent, Johann ;
Bomel, Pierre ;
Rossi, Andre ;
Boutillon, Emmanuel ;
Palesi, Maurizio .
2017 27TH INTERNATIONAL SYMPOSIUM ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS), 2017,
[42]   PhoNoCMap: an Application Mapping Tool for Photonic Networks-on-Chip [J].
Fusella, Edoardo ;
Cilardo, Alessandro .
PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, :289-292
[43]   A Real-Time Java']Java Chip-Multiprocessor [J].
Pitter, Christof ;
Schoeberl, Martin .
ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2010, 10 (01)
[44]   Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Networks-on-Chip [J].
Bertozzi, Davide ;
Miorandi, Gabriele ;
Tala, Mahdi ;
Nowick, Steven M. .
2017 FIRST NEW GENERATION OF CAS (NGCAS), 2017, :77-80
[45]   A fault-tolerant and congestion-aware architecture for wireless networks-on-chip [J].
Mortazavi, Seyed Hassan ;
Akbar, Reza ;
Safaei, Farshad ;
Rezaei, Amin .
WIRELESS NETWORKS, 2019, 25 (06) :3675-3687
[46]   A Flexible Parallel Simulator for Networks-on-Chip With Error Control [J].
Yu, Qiaoyan ;
Ampadu, Paul .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2010, 29 (01) :103-116
[47]   Bit-accurate energy estimation for Networks-on-Chip [J].
Moreac, Erwan ;
Rossi, Andre ;
Laurent, Johann ;
Bomel, Pierre .
JOURNAL OF SYSTEMS ARCHITECTURE, 2017, 77 :112-124
[48]   Adaptive Networks-on-Chip Routing with Fuzzy Logic Control [J].
Tatas, K. ;
Chrysostomou, C. .
19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016), 2016, :138-145
[49]   Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors [J].
Wang, Zhehui ;
Xu, Jiang ;
Wu, Xiaowen ;
Ye, Yaoyao ;
Zhang, Wei ;
Nikdast, Mahdi ;
Wang, Xuan ;
Wang, Zhe .
IEEE TRANSACTIONS ON COMPUTERS, 2014, 63 (06) :1445-1458
[50]   Power efficient network selector placement in control plane of multiple networks-on-chip [J].
Yadav, Sonal ;
Raj, Ritu .
JOURNAL OF SUPERCOMPUTING, 2022, 78 (05) :6664-6695