A 128-Gb/sD-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET

被引：11

作者：

Agrawal, Abhishek ^{[1
]}

Whitcombe, Amy ^{[2
]}

Shin, Woorim ^{[1
,3
]}

Bhat, Ritesh ^{[1
]}

Kundu, Somnath ^{[1
,4
]}

Sagazio, Peter ^{[1
]}

Chandrakumar, Hariprasad ^{[5
]}

Brown, Thomas W. ^{[5
]}

Carlton, Brent R. ^{[1
]}

Hull, Christopher ^{[1
,6
]}

Callender, Steven ^{[1
]}

Pellerano, Stefano ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

[2] Intel Corp, Santa Clara, CA 95054 USA

[3] Apple, Cupertino, CA 95014 USA

[4] AMD, Hillsboro, OR 97123 USA

[5] Intel Corp, Adv Design Grp Technol Dev Org, Hillsboro, OR 97124 USA

[6] Amazon, Redmond, WA 98052 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2023年 / 58卷 / 12期

关键词：

Analog-to-digital converter (ADC); CMOS; FinFET; low-noise amplifier (LNA); phase-locked loop (PLL); receiver (RX); sub-terahertz (subTHz); wideband; BAND; OPTIMIZATION; DESIGN;

D O I：

10.1109/JSSC.2023.3315692

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents aD-band (110-170 GHz) receiver (RX) with integrated analog-to-digital converter (ADC) and phase-locked loop (PLL). The receiver front end (RXFE) consists of a coupled-line-based Guanella balun matching network, 140-GHz low-noise amplifier (LNA), and Cherry-Hooper (CH) amplifier providing >20-GHz baseband bandwidth. A quadrature PLL provides I/Q local oscillator (LO) signals for down-conversion. Two 32-GS/s hybrid voltage- and time-domain ADCs digitize the RXFE output. The fully integrated 22-nm FinFET CMOS prototype achieves a peak data rate of 128 Gb/s using 16-QAM modulation with-15.2-dB EVM and consumes 246 mW for 1.95-pJ/b efficiency. The stand-alone RXFE without ADC provides 160-Gb/s data rates with-16.4-dB EVM and consumes 166 mW for 1.04-pJ/b efficiency

引用

页码：3364 / 3379

页数：16

共 46 条

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