An Efficient Hardware Design of Prime Field Modular Inversion/Division for Public Key Cryptography

In this paper, we proposed an area-efficient hardware implementation of modular inversion/division, which is a complex and crucial component in elliptic curve cryptography (ECC). Our modular inversion/division is based on our modified binary inversion algorithm. The proposed hardware implementation of modular inversion/division improves the area efficiency and was designed and implemented on Xilinx Spartan-6 and Virtex-7 field-programmable gate array (FPGA) platforms and simulated with TSMC 90nm and 180nm technology nodes. Our proposed modular inversion/division is suitable for prime fields used in public key cryptography, including the NIST-recommended elliptic curves. It occupies 618 slices and 607 slices in Xilinx Spartan-6 and Virtex-7 FPGA platform, computes in 10.6 mu s and 6.45 over the prime filed P-256, at a maximum operating frequency of 33.76 MHz and 55.49 MHz. It occupies 23997 GE and 28471 GE, computes in 1.25 mu s and 2.43 mu s over the prime fields P-256 at a maximum operating frequency of 285.71 MHz and 147.06 MHZ, respectively for TSMC 90nm and 180nm technology node implementation.