Delay based hardware Trojan detection exploiting spatial correlations to suppress variations

被引:1
作者
Esirci, Fatma Nur [1 ]
Bayrakci, Alp Arslan [1 ]
机构
[1] Gebze Tech Univ, Dept Comp Engn, Kocaeli, Turkiye
关键词
Hardware security; Hardware Trojan; Side-channel analysis; Delay based detection; Spatial correlation; STATISTICAL TIMING ANALYSIS; IMPACT;
D O I
10.1016/j.vlsi.2023.03.006
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Hardware Trojan detection is a crucial problem with many dimensions and high complexity. Side channel analysis based methods are advantageous for not requiring Trojan activation but deeply suffer from process variations, the inability to detect small Trojans as well as the requirement for golden chips. In this paper, a non-invasive, golden chip free delay based hardware Trojan detection method is proposed. It exploits the inherent spatial correlations to suppress the Trojan hiding effect of the variations. The method is verified using post-manufacturing simulations under an elaborative variation model considering both inter and intra die components. The results reveal that although delay-alone approach fails to detect minimal Trojans, the proposed method achieves the detection securing more than 91% percent of a circuit on average. Moreover, if the trigger detection in cooperation with the payload detection is utilized, the detection probability exceeds 99%.
引用
收藏
页码:107 / 118
页数:12
相关论文
共 37 条
[21]  
Li J, 2008, 2008 IEEE INTERNATIONAL WORKSHOP ON HARDWARE-ORIENTED SECURITY AND TRUST, P8, DOI 10.1109/HST.2008.4559038
[22]  
Lov L., 1993, Paul erdos is eighty, V2, P4
[23]  
Maechler M., 2021, diptest: Hartigan's Dip Test Statistic for Unimodality - Corrected
[24]  
Mitra S., 2015, Stopping hardware Trojans in their tracks
[25]  
N.C.S. University, 2008, NANGATE 45NM OP CELL
[26]   Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis [J].
Narasimhan, Seetharam ;
Du, Dongdong ;
Chakraborty, Rajat Subhra ;
Paul, Somnath ;
Wolff, Francis G. ;
Papachristou, Christos A. ;
Roy, Kaushik ;
Bhunia, Swarup .
IEEE TRANSACTIONS ON COMPUTERS, 2013, 62 (11) :2183-2195
[27]  
S.I. Association, 2011, INT TECHNOLOGY ROADM
[28]  
Sutherland I., 1999, Logical effort: designing fast CMOS circuits
[29]   Variability in nanometer CMOS: Impact, analysis, and minimization [J].
Sylvester, Dennis ;
Agarwal, Kanak ;
Shah, Saumil .
INTEGRATION-THE VLSI JOURNAL, 2008, 41 (03) :319-339
[30]   A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach [J].
Taheri, Hamidreza Esmaeili ;
Mirhassani, Mitra .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 30 (03) :315-324