A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks

This article presents a novel generalized approach to obtain rational (dyadic and integer) bi-orthogonal wavelet filter coefficients based on two conditions, namely maximally flatness and near-perfect reconstruction (PR) in half-band polynomial (HBP). An incremental-iterative approach is adopted to design the coefficients based on the proposed error equation in terms of the remainder polynomial (RP) of Lagrange HBP and the proposed HBP with maximum vanishing moments (VMs). In addition, VLSI architecture for the proposed wavelet filter banks (FBs) is designed and implemented on the Zedboard ZYNQ-7000 AP-SoC (Zynq FPGA from Xilinx) field-programmable gate array. It is found that the proposed rationalized wavelet FBs achieved significantly low digital hardware requirements with similar characteristics when compared to well-known rationalized existing bi-orthogonal wavelet FBs. The effectiveness of the designed wavelet FBs is verified in image compression and image retrieval on well-known publicly available databases. It is found that the designed rationalized bi-orthogonal wavelet FBs give better performances when compared to existing rationalized bi-orthogonal wavelet FBs.