A DTC-Free Fractional-N BBPLL With FIR-Embedded Injection-Locked-Oscillator-Based Phase-Domain Lowpass Filter

被引:1
作者
Feng, Liqun [1 ]
Rhee, Woogeun [1 ]
Wang, Zhihua [1 ]
机构
[1] Tsinghua Univ, Sch Integrated Circuits, Beijing 100084, Peoples R China
关键词
Frequency modulation; Filtering; Quantization (signal); Finite impulse response filters; Frequency-domain analysis; Transfer functions; Phase locked loops; Delta Sigma quantization noise; bang-bang PLL (BBPLL); finite-impulse response (FIR) filter; fractional-N; injection-locked oscillator (ILO); phase-domain lowpass filter (PDLPF); MODULATOR; LOCKING; DESIGN; SYNTHESIZER; RECEIVER;
D O I
10.1109/JSSC.2023.3343952
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The all-digital fractional-N bang-bang PLL (BBPLL) requires a high-resolution digital-to-time converter (DTC) with complex nonlinearity calibration or compensation. For the design of a DTC-free Delta Sigma fractional-N BBPLL, the use of a phase-domain lowpass filter (PDLPF) based on a finite-impulse response (FIR)-embedded injection-locked oscillator (FIR-ILO) is proposed. By integrating the FIR filtering in the ILO-based PDLPF, the quantization noise effect of the Delta Sigma modulator is significantly mitigated in the fractional-N BBPLL, resulting in good in-band phase noise and fractional spur performance. A prototype fractional-N BBPLL is implemented in 65-nm CMOS. With the proposed FIR-ILO PDLPF, the in-band phase noise and the fractional spur are improved by more than 25 and 10 dB, respectively. An in-band noise of -96.6 dBc/Hz and a reference spur of -78.7 dBc are achieved at 2.6-GHz output, consuming 4.3 mW from a 0.9-V supply. The proposed FIR-ILO filtering method is useful not only to improve the in-band noise and spur of the fractional-N BBPLL but also to provide an effective way of suppressing the out-of-band noise for conventional fractional-N PLLs.
引用
收藏
页码:728 / 739
页数:12
相关论文
共 43 条
[1]   A STUDY OF LOCKING PHENOMENA IN OSCILLATORS [J].
ADLER, R .
PROCEEDINGS OF THE INSTITUTE OF RADIO ENGINEERS, 1946, 34 (06) :351-357
[2]   A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs [J].
Avallone, Luca ;
Mercandelli, Mario ;
Santiccioli, Alessio ;
Kennedy, Michael Peter ;
Levantino, Salvatore ;
Samori, Carlo .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 68 (07) :2775-2786
[3]   Analysis and design of wideband injection-locked ring oscillators with multiple-input injection [J].
Chien, Jun-Chau ;
Lu, Liang-Hung .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (09) :1906-1915
[4]   A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration [J].
Choo, Min-Seong ;
Kim, Sungwoo ;
Ko, Han-Gon ;
Cho, Sung-Yong ;
Park, Kwanseo ;
Lee, Jinhyung ;
Shin, Soyeong ;
Chi, Hankyu ;
Jeong, Deog-Kyoon .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56 (08) :2525-2538
[5]   A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time [J].
Dartizio, Simone M. ;
Buccoleri, Francesco ;
Tesolin, Francesco ;
Avallone, Luca ;
Santiccioli, Alessio ;
Iesurum, Agata ;
Steffan, Giovanni ;
Cherniak, Dmytro ;
Bertulessi, Luca ;
Bevilacqua, Andrea ;
Samori, Carlo ;
Lacaita, Andrea L. ;
Levantino, Salvatore .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57 (12) :3538-3551
[6]  
Deng WB, 2015, INTERNATIONAL CONFERENCE ON MECHANICS AND CONTROL ENGINEERING (MCE 2015), P1
[7]   Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers [J].
Elkholy, Ahmed ;
Talegaonkar, Mrunmay ;
Anand, Tejasvi ;
Hanumolu, Pavan Kumar .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (12) :3160-3174
[8]  
Feng L., 2023, PROC IEEE CUSTOM INT, P1
[9]   A Quantization Noise Reduction Method for Delta-Sigma Fractional-N PLLs Using Cascaded Injection-Locked Oscillators [J].
Feng, Liqun ;
Rhee, Woogeun ;
Wang, Zhihua .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 69 (05) :2448-2452
[10]   A 32-GHz Nested-PLL-Based FMCW Modulator With 2.16-GHz Bandwidth in a 65-nm CMOS Process [J].
Fu, Yupeng ;
Li, Lianming ;
Liao, Yilong ;
Wang, Xuan ;
Shi, Yongjian ;
Wang, Dongming .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2020, 28 (07) :1600-1609