Carry Disregard Approximate Multipliers

被引:10
作者
Amirafshar, Nima [1 ]
Baroughi, Ahmad Sadigh [1 ]
Shahhoseini, Hadi Shahriar [1 ]
Taherinejad, Nima [2 ,3 ]
机构
[1] Iran Univ Sci & Technol, Sch Elect Engn, Tehran 1311416846, Iran
[2] Heidelberg Univ, Inst Comp Engn, D-69117 Heidelberg, Germany
[3] TU Wien, Inst Comp Technol ICT, A-1040 Vienna, Austria
关键词
Delays; Computer architecture; Power demand; Adders; Logic gates; Hardware; Approximate computing; carry disregard multiplier; power-efficient; image processing; 4-2; COMPRESSORS; DESIGN; POWER; ADDERS;
D O I
10.1109/TCSI.2023.3306071
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Several challenges in improving the performance of computing systems have given rise to emerging computing paradigms. One of these paradigms is approximate computing. Many applications require different levels of accuracy and are error-tolerance to a certain degree. Approximate computations can reduce the calculation complexities significantly and thus improve the performance. Here, we propose a methodology for designing approximate N-bit array multipliers based on carry disregarding. We evaluate and analyze the proposed multipliers both experimentally and theoretically. The proposed 8-bit multipliers, compared to the exact multiplier, reduce the critical path delay, power consumption, and area by 29%, 29%, and 30%, on average. Compared to the existing approximate array architectures in the literature, they have improved 14.3%, 22.8%, and 26.4%, respectively. Compared to the exact 16-bit multiplier, the proposed 16-bit multipliers have reduced the delay, power consumption, and area by 35%, 24%, and 23% on average. In an image processing application, we have also demonstrated the applicability of a wide range of proposed multipliers, which have Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) over 30 dB and 94%, respectively.
引用
收藏
页码:4840 / 4853
页数:14
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