Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks

被引:6
|
作者
Bai, Yueyin [1 ]
Zhou, Hao [1 ]
Zhao, Keqing [1 ]
Chen, Jianli [1 ]
Yu, Jun [1 ]
Wang, Kun [1 ]
机构
[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China
关键词
D O I
10.1109/FCCM57271.2023.00049
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Existing implementations of transformer networks by field-programmable gate array (FPGA) focus only on attention computation, or suffer from fixed model structure without flexibility. In this article, we propose an FPGA-based overlay processor, named Transformer-OPU for general accelerations of transformer networks. Experimental result shows that our Transformer-OPU achieves 5.19-15.06x and 1.14-2.89x speedup compared with CPU and GPU, respectively. We also observe 1.10-2.47x better latency compared with previously customized FPGA accelerators, and is 1.45x faster than NPE.
引用
收藏
页码:222 / 222
页数:1
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