A high efficiency buck converter based on PLL for frequency stabilization

A high efficiency Buck converter circuit based on Phase-locked loop (PLL) to achieve frequency stabilization is proposed to solve the problems of reduced converter efficiency, unstable output and high electromagnetic interference caused by unstable switching frequency. Since the increase of load current increases the switching frequency in the conventional adaptive on-time (AOT) control, a phase-locked loop is designed to achieve the switching frequency stabilization by forming a negative feedback. In addition, a bootstrap high-voltage gate driver circuit is designed to drive the dual NMOS power tubes in order to achieve high conversion efficiency and optimize the chip area. The proposed Buck circuit is simulated and verified based on SMIC 0.18 mu m CMOS 2P4M process, with an input voltage of 2.5V-5.5V, an output voltage of 0.8V-4V, a switching frequency variation rate of only 8.5 kHz/A over the load range of 0.5A-3A, and a peak efficiency of 94.8 % over the full load range is achieved, and the undershoot/overshoot recovery time of the load transient response is only 5.4 mu s and 6.9 mu s.