A low-power charge-based integrate-and-fire circuit for binarized-spiking neural network

被引:3
作者
Duong, Quang-Manh [1 ]
Trinh, Quang-Kien [1 ]
Nguyen, Van-Tinh [1 ]
Dao, Dinh-Ha [1 ]
Luong, Duy-Manh [1 ]
Hoang, Van-Phuc [2 ]
Lin, Longyang [3 ]
Deepu, John [4 ]
机构
[1] Le Quy Don Tech Univ, Fac Radioelect Engn, Hanoi, Vietnam
[2] Le Quy Don Tech Univ, Inst Syst Integrat, Hanoi, Vietnam
[3] Southern Univ Sci & Technol, Sch Microelect, Shenzhen, Peoples R China
[4] Univ Coll Dublin, Sch Elect & Elect Engn, Dublin, Ireland
基金
欧盟地平线“2020”;
关键词
binary spiking neural networks; in-memory computing; neuromorphic computing; STT-MRAM;
D O I
10.1002/cta.3573
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a charge-based integrate-and-fire (IF) circuit for in-memory binary spiking neural networks (BSNNs). The proposed IF circuit can mimic both addition and subtraction operations that permit better incorporation with in-memory XNOR-based synapses to implement the BSNN processing core. To evaluate the proposed design, we have developed a framework that incorporates the circuit's imperfections effects into the system-level simulation. The array circuits use 2T-2J Spin-Transfer-Torque Magnetoresistive RAM (STT-MRAM) based on a 65-nm commercial CMOS and a fitted magnetic tunnel junction (MTJ). The system model has been described in Pytorch to best fit the extracted parameters from circuit levels, including the cover of device nonidealities and process variations. The simulation results show that the proposed design can achieve a performance of 5.10 fJ/synapse and reaches 82.01% classification accuracy for CIFAR-10 under process variation.
引用
收藏
页码:3404 / 3414
页数:11
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