Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition

被引：0

作者：

Liu, Bo ^{[1
]}

Cai, Hao ^{[1
]}

Zhang, Zilong ^{[1
]}

Ding, Xiaoling ^{[1
]}

Zhang, Renyuan ^{[1
]}

Gong, Yu ^{[1
]}

Wang, Zhen ^{[2
]}

Ge, Wei ^{[1
]}

Yang, Jun ^{[1
]}

机构：

[1] Southeast Univ, Natl ASIC Syst Engn Ctr, Nanjing 210096, Peoples R China

[2] Nanjing Prochip Elect Technol Co Ltd, Nanjing 210001, Peoples R China

来源：

IEEE DESIGN & TEST | 2023年 / 40卷 / 03期

基金：

国家重点研发计划;

关键词：

Encoding; Power demand; Adders; Tensors; Convolutional neural networks; Computer architecture; Speech recognition; Approximate tensor multiplication; complementary compensation encoding; precision reconfigurable approximate computing; keywords speech recognition;

D O I：

10.1109/MDAT.2021.3135346

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Editor's notes: A circuit architecture is designed to utilize Booth encoding for the multiplication of two vectors of data. This architecture is configured to use approximate encoding and addition and a lower voltage for the approximate circuits to improve energy efficiency. Integrating this design into a convolutional neural network leads to a rather significant reduction in energy with a slight accuracy loss for speech recognition. -Jie Han, University of Alberta

引用

页码：26 / 35

页数：10

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