Voltage Acceleration of Power NLDMOS Hot Carrier Degradation

Hot carrier degradation (HCD) acceleration phenomenon by stress drain-source voltage of HV power NLDMOS devices have been studied using automated wafer level test methodology. A reasonable confidence level of the accelerated degradation rate prediction extrapolated from short term test results is demonstrated for the range of stress voltages between maximum operation voltage (MOV) and physical absolute maximum rating (AMR) determined through pulsed safe operating area (SOA). Two architectures of the HV power optimized NLDMOS devices are compared to LV NMOS. The applicability of high similar to 100x acceleration factor is demonstrated to enable full wafer data collection for statistical variation of the long-term reliability parameters for different wafer lots and device versions.