A Deep-Learning Data-Driven Approach for Reducing FPGA Routing Runtimes

Many researchers have identified the long run-time of Field Programmable Gate Array (FPGA) routing tools as a major barrier to the timely completion of designs. This paper presents a robust, data-driven method for reducing routing run-time that requires no changes to the routing algorithm and that preserves solution quality. The approach involves first predicting the global switch and wire-segment utilization for a given placement, and then pre-loading this information into the router changing the node pricing used by the negotiationcongested heuristic employed by the router. This foresight enables the router to make alternate decisions early on, resulting in faster convergence. The forecasting of routing-resource utilization is formulated as an image-translation problem and resolved using a convolutional encoder decoder with modified loss function. The deep-learning model is trained and tested using the large, modern Titan benchmarks. The proposed approach is applied to two state-of-the-art FPGA routers, AIR and Enhanced Pathfinder, and adds almost no computational overhead to either router. Empirical results show an average reduction in CPU runtimes of 17.3% and 44.3% for AIR and Enhanced Pathfinder, respectively, with no significant degradation in wirelength or critical-path delay.