eVeriCombTest: Automated Test Case Generation Technique Using a Combination of Verification and Combinatorial Testing

被引：0
作者：
Godboley, Sangharatna [1 ]
机构：
[1] Natl Inst Technol Warangal, Dept Comp Sci & Engn, Warangal, Telangana, India
来源：
PROCEEDINGS OF THE 18TH INTERNATIONAL CONFERENCE ON EVALUATION OF NOVEL APPROACHES TO SOFTWARE ENGINEERING, ENASE 2023 | 2023年
关键词：
Verification; Combinatorial Testing; Test Cases; Mutation Analysis;
D O I：
10.5220/0011758700003464
中图分类号：
TP31 [计算机软件];
学科分类号：
081202 ; 0835 ;
摘要：
We propose VeriCombTest which is the combination of Verification and Combinatorial Testing. We experimented with 38 C-Programs from The RERS challenge repository. Verification (CBMC) produced 940 test cases and Combinatorial Testing (PICT) populated a total of 42053 test cases. The good point is that for 40 programs, PICT consumed only 2.6 Minutes to populate the test inputs, however, CBMC which is a Static Symbolic Executor consumed 546.99 Minutes to generate the test inputs. We performed mutation analysis for this work. VeriCombTest has 355 extra killed mutants as compared to the baseline. VeriCombTest is a fully automated tool.
引用
收藏
页码：306 / 313
页数：8
相关论文
共 11 条
  • [1] VeriAbs : Verification by Abstraction and Test Generation
    Afzai, Mohammad
    Asia, A.
    Chauhan, Avriti
    Chimdyalwar, Bharti
    Darke, Priyanka
    Datar, Advaita
    Kumar, Shrawan
    Venkatesh, R.
    [J]. 34TH IEEE/ACM INTERNATIONAL CONFERENCE ON AUTOMATED SOFTWARE ENGINEERING (ASE 2019), 2019, : 1138 - 1141
  • [2] Armando A, 2006, LECT NOTES COMPUT SC, V3925, P146
  • [3] Enhancing Symbolic Execution with Veritesting
    Avgerinos, Thanassis
    Rebert, Alexandre
    Cha, Sang Kil
    Brumley, David
    [J]. 36TH INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING (ICSE 2014), 2014, : 1083 - 1094
  • [4] VeriFuzz: Program Aware Fuzzing (Competition Contribution)
    Chowdhury, Animesh Basak
    Medicherla, Raveendra Kumar
    Venkatesh, R.
    [J]. TOOLS AND ALGORITHMS FOR THE CONSTRUCTION AND ANALYSIS OF SYSTEMS, PT III, 2019, 11429 : 244 - 249
  • [5] Clarke E., 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451), P368
  • [6] VeriAbs: Verification by Abstraction and Test Generation
    Darke, Priyanka
    Prabhu, Sumanth
    Chimdyalwar, Bharti
    Chauhan, Avriti
    Kumar, Shrawan
    Basakchowdhury, Animesh
    Venkatesh, R.
    Datar, Advaita
    Medicherla, Raveendra Kumar
    [J]. TOOLS AND ALGORITHMS FOR THE CONSTRUCTION AND ANALYSIS OF SYSTEMS, TACAS 2018, PT II, 2018, 10806 : 457 - 462
  • [7] Mall R., 2018, Fundamentals of Software Engineering
  • [8] Mathur A. P., 1993, Comparing the fault detection e ectiveness of mutation and data flow testing: An empirical study
  • [9] A Survey of Combinatorial Testing
    Nie, Changhai
    Leung, Hareton
    [J]. ACM COMPUTING SURVEYS, 2011, 43 (02)
  • [10] RERS, 2018, RERS
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