Analysing Mismatch effect of CMOS Neurons in Spiking Neural Network with Winner-take-all Mechanism

The aim of designing the energy-efficient highdensity spiking neural network (SNN) is not possible without channelising the efforts to design the basic repeating blocks of Neuromorphic Computing (NMC), i.e., neurons and synapses. The investigation done to replace synapses in the last years has created memristors as the most prominent solution for high-density SNN. CMOS-memristive integrated circuits are widely adopted to realise brain-inspired neuromorphic circuits. While the challenges of the memristors have been highlighted and resolved in various literature, much attention is not given to designing robust CMOS neurons and its challenges for achieving high-density integration in neuromorphic chips. Process-induced variations must be analysed for the robustness of the CMOS neurons. Apart from the process and temperature variations of CMOS neuron, which is mostly analysed in previous works, mismatches are critical for the SNN with a winner-take-all (WTA) mechanism where output neurons compete to win the competition. In this paper, we have shown that the SNN with WTA mechanism is robust to PVT variations but is sensitive to mismatch variations of CMOS neurons. We have also proposed an approach to mitigate the mismatch effect. The observations are validated with the post-layout simulation results of the SNN circuit designed in 180 nm CMOS technology.