Enhancing the lifetime of STT-RAM using compression based wear leveling technique

Driven memory requirements have increased with the increase in processor core count and working sets. Con-ventional memory technology such as SRAM (static random access memory) is unable to fulfill these demands. Alternate memory technologies such as NVM (non-volatile memory) have been proposed to fulfill the demands of higher memory usage due to its huge storage capacity and less leakage power. Though NVM is having the above advantages, it is limited in performance due to write restrictions. The write restriction directly affects the cache lifetime, which is an important parameter for computer system performance. This paper explores a compression based wear leveling technique to overcome the limitations of write restriction and to improve the cache lifetime. The proposed method lessens the bit writes to be written and also distributes the write equally in the sets of the cache. The frequent pattern compression is used to reduce each word write based on defined pattern sets. The writes are spread within word to enable uniform distribution of writes. The bit transitions during the writes can be reduced further by identifying the existing cache line with minimum transitions to be placed. Wear leveling is implemented to enhance the cache endurance by equally distributing the incoming writes to all the cache blocks. The proposed method improves the lifespan by 42 %, 52 %, 75 % and 18 % with a 5 % area overhead compared to LER, TA_LRU, Equalwrites and Compression+EW techniques.