High-speed SABER key encapsulation mechanism in 65nm CMOS

被引：8

作者：

Imran, Malik ^{[1
]}

Almeida, Felipe ^{[1
]}

Basso, Andrea ^{[2
]}

Roy, Sujoy Sinha ^{[3
]}

Pagliarini, Samuel ^{[1
]}

机构：

[1] Tallinn Univ Technol, Dept Comp Syst, Tallinn, Estonia

[2] Univ Birmingham, Sch Comp Sci, Birmingham, England

[3] Graz Univ Technol, IAIK, Graz, Austria

来源：

JOURNAL OF CRYPTOGRAPHIC ENGINEERING | 2023年 / 13卷 / 04期

基金：

欧盟地平线“2020”;

关键词：

ASIC; Post-quantum; Crypto accelerator; Silicon-proven; SABER;

D O I：

10.1007/s13389-023-00316-2

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Quantum computers will break cryptographic primitives that are based on integer factorization and discrete logarithm problems. SABER is a key agreement scheme based on the Learning With Rounding problem that is quantum-safe, i.e., resistant to quantum computer attacks. This article presents a high-speed silicon implementation of SABER in a 65nm technology as an Application Specific Integrated Circuit. The chip measures 1mm(2) in size and can operate at a maximum frequency of 715MHz at a nominal supply voltage of 1.2V. Our chip takes 10, 9.9 and 13 mu s for the computation of key generation, encapsulation, and decapsulation operations of SABER. The average power consumption of the chip is 153.6mW. Physical measurements reveal that our design is 8.96x (for key generation), 11.80x (for encapsulation), and 11.23x (for decapsulation) faster than the best known silicon-proven SABER implementation.

引用

页码：461 / 471

页数：11