A 12-bit single slope ADC with multi-step structure and ramp calibration technique for image sensors

This paper presents a novel multi-step single slope analog to digital converter (MS SS ADC). The proposed ADC splits the 12-bit conversion into 3 steps, including 1-bit half section decision, 4-bit coarse conversion, and finally 8-bit fine conversion with 1-bit redundancy. The conversion step is substantially reduced from conventional 4096 to 276. The linearity of the ADC is guaranteed by a stable common mode voltage of the comparator varying only within 31.25 mV. Moreover, two high-accuracy ramp calibration techniques are utilized to correct the current variation in the fine ramp and the slope error between the coarse and fine ramps. A hybrid comparator is utilized in the ADC to save power while maintaining the performance. The ADC is designed and simulated in 0.18 & mu;m CMOS process with 7.5 & mu;m width. The differential nonlinearity and integral nonlinearity of the proposed ADC are reduced from +0.3/-1 LSB and +3.1/-2.55 LSB to +0.3/-0.3 LSB and +1/-0.45 LSB at 61.7 kS/s sample rate by the calibrations.