Segment Reduction-Based Space Vector Pulse Width Modulation for a Three-Phase F-Type Multilevel Inverter with Reduced Harmonics and Switching States

An improved segment reduction-based space vector pulse width modulation (SVPWM) for an F-type three-level inverter (FT2LI) is presented in this article. The proposed SVPWM algorithm decreases the additional switching state transition of each triangle with the application of an improved nine- and three-segment reduction switching strategy. The main feature of the segment reduction technique is that it eliminates second-order harmonics in the inverter output side with good total harmonic distortion (THD), low switching losses, and minimum filter requirements when compared with carrier-based PWM (CBPWM) techniques such as multi-carrier sine PWM (MC-SPWM), sixty-degree PWM (60 degrees PWM), and switching frequency optimal PWM (SFO PWM). The proposed modulation algorithm for FT2LI is implemented on the MATLAB/Simulink platform. The performance of the proposed segment reduction-based SVPWM algorithm is tested experimentally on an FT2LI at various amplitude and frequency modulation indices, and the experimental results are verified with the simulation results. Additionally, a comparative analysis carried out to study the relationship between the segment reduction-based SVPWM and CBPWM techniques inferred that the suggested segment reduction-based SVPWM algorithms can optimize high-order harmonic distributions and have a minimum computational burden.