An accurate Verilog-A based model for MEMS capacitive accelerometer

This paper presents an accurate macro model for a capacitive micro accelerometer using Verilog-A tool. For this purpose, first the accelerometer is simulated in COMSOL software. Then, considering the simplified physics of the accelerometer, a preliminary Verilog-A model is derived, which is not accurate enough. This initial model has been modified by using mathematical tools and adapting to the results of COMSOL. Furthermore, a switched-capacitor based capacitance to voltage converter (CVC) is used as a readout circuit to validate the proposed model. The CVC is designed, simulated and optimized in the Cadence software by using a 65 nm CMOS tech-nology. In order to reduce low-frequency non-idealities such as flicker noise and DC offsets, a chopper-stabilization technique is used. The power consumption for a 1.2 V supply is 140 & mu;W. Simulation results show a good agreement between COMSOL results and simulation of the proposed model in the Cadence.