An accurate Verilog-A based model for MEMS capacitive accelerometer

被引：1

作者：

Vajargah, Maryam Karimi ^{[1
]}

Shamsi, Hossein ^{[1
]}

机构：

[1] KN Toosi Univ Technol, Fac Elect Engn, Microelect Circuits Lab, Tehran, Iran

来源：

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2023年 / 164卷

关键词：

Accelerometer; Verilog-A model; MEMS capacitive; Readout Circuit; Capacitance to Voltage Converter; CONVERTER; SENSOR; DESIGN; OFFSET;

D O I：

10.1016/j.aeue.2023.154625

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an accurate macro model for a capacitive micro accelerometer using Verilog-A tool. For this purpose, first the accelerometer is simulated in COMSOL software. Then, considering the simplified physics of the accelerometer, a preliminary Verilog-A model is derived, which is not accurate enough. This initial model has been modified by using mathematical tools and adapting to the results of COMSOL. Furthermore, a switched-capacitor based capacitance to voltage converter (CVC) is used as a readout circuit to validate the proposed model. The CVC is designed, simulated and optimized in the Cadence software by using a 65 nm CMOS tech-nology. In order to reduce low-frequency non-idealities such as flicker noise and DC offsets, a chopper-stabilization technique is used. The power consumption for a 1.2 V supply is 140 & mu;W. Simulation results show a good agreement between COMSOL results and simulation of the proposed model in the Cadence.

引用

页数：10

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