Survey of Reliability Research on 3D Packaged Memory

被引:7
作者
Zhou, Shuai [1 ,2 ]
Ma, Kaixue [1 ]
Wu, Yugong [1 ]
Liu, Peng [2 ]
Hu, Xianghong [2 ]
Nie, Guojian [2 ]
Ren, Yan [2 ]
Qiu, Baojun [2 ]
Cai, Nian [3 ]
Xu, Shaoqiu [3 ]
Wang, Han [3 ]
机构
[1] Tianjin Univ, Sch Microelect, Tianjin 300072, Peoples R China
[2] China Elect Prod Reliabil & Environm Testing Res I, Guangzhou 510610, Peoples R China
[3] Guangdong Univ Technol, Sch Informat Engn, Guangzhou 510006, Peoples R China
关键词
3D packaging; memory; environmental load; reliability; review; SOLDER JOINT RELIABILITY; ON-PACKAGE; STACKING; BEHAVIOR; STRESS; DESIGN; MODEL; SIMULATION; DIFFUSION; SILICON;
D O I
10.3390/electronics12122709
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
As the core carrier of information storage, a semiconductor memory device is a basic product with a large volume that is widespread in the integrated circuit industry. With the rapid development of semiconductor manufacturing processes and materials, the internal structure of memory has gradually shifted from a 2D planar packaging structure to a 3D packaging structure to meet industry demands for high-frequency, high-speed, and large-capacity devices with low power consumption. However, advanced 3D packaging technology can pose some reliability risks, making devices prone to failure, especially when used in harsh environmental conditions, including temperature changes, high temperature and humidity levels, and mechanical stress. In this paper, the authors introduce the typical structure characteristics of 3D packaged memory; analyze the reasons for device failure caused by stress; summarize current research methods that utilize temperature, mechanical and hygrothermal theories, and failure models; and present future challenges and directions regarding the reliability research of 3D packaged memory.
引用
收藏
页数:49
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