RVComp: Analog Variation Compensation for RRAM-based In-Memory Computing
被引:2
|
作者:
He, Jingyu
论文数: 0引用数: 0
h-index: 0
机构:
Hong Kong Univ Sci & Technol, Hong Kong, Peoples R ChinaHong Kong Univ Sci & Technol, Hong Kong, Peoples R China
He, Jingyu
[1
]
Lastras, Miguel
论文数: 0引用数: 0
h-index: 0
机构:
Univ Autonoma San Luis Potosi, San Luis Potosi, San Luis Potosi, MexicoHong Kong Univ Sci & Technol, Hong Kong, Peoples R China
Lastras, Miguel
[2
]
Ye, Terry Tao
论文数: 0引用数: 0
h-index: 0
机构:
Southern Univ Sci & Technol, Shenzhen, Peoples R ChinaHong Kong Univ Sci & Technol, Hong Kong, Peoples R China
Ye, Terry Tao
[3
]
Tsui, Chi-Ying
论文数: 0引用数: 0
h-index: 0
机构:
Hong Kong Univ Sci & Technol, Hong Kong, Peoples R ChinaHong Kong Univ Sci & Technol, Hong Kong, Peoples R China
Tsui, Chi-Ying
[1
]
Cheng, Kwang-Ting
论文数: 0引用数: 0
h-index: 0
机构:
Hong Kong Univ Sci & Technol, Hong Kong, Peoples R ChinaHong Kong Univ Sci & Technol, Hong Kong, Peoples R China
Cheng, Kwang-Ting
[1
]
机构:
[1] Hong Kong Univ Sci & Technol, Hong Kong, Peoples R China
[2] Univ Autonoma San Luis Potosi, San Luis Potosi, San Luis Potosi, Mexico
[3] Southern Univ Sci & Technol, Shenzhen, Peoples R China
来源:
2023 28TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC
|
2023年
关键词:
Resistive random access memory;
reliability;
analog compensation;
INFERENCE;
MODEL;
D O I:
10.1145/3566097.3567858
中图分类号:
TP [自动化技术、计算机技术];
学科分类号:
0812 ;
摘要:
Resistive Random Access Memory (RRAM) has shown great potential in accelerating memory-intensive computation in neural network applications. However, RRAM-based computing suffers from significant accuracy degradation due to the inevitable device variations. In this paper, we propose RVComp, a fine-grained analog Compensation approach to mitigate the accuracy loss of in-memory computing incurred by the Variations of the RRAM devices. Specifically, weights in the RRAM crossbar are accompanied by dedicated compensation RRAM cells to offset their programming errors with a scaling factor. A programming target shifting mechanism is further designed with the objectives of reducing the hardware overhead and minimizing the compensation errors under large device variations. Based on these two key concepts, we propose double and dynamic compensation schemes and the corresponding support architecture. Since the RRAM cells only account for a small fraction of the overall area of the computing macro due to the dominance of the peripheral circuitry, the overall area overhead of RVComp is low and manageable. Simulation results show RVComp achieves a negligible 1.80% inference accuracy drop for ResNet18 on the CIFAR-10 dataset under 30% device variation with only 7.12% area and 5.02% power overhead and no extra latency.