A low-temperature photoresist-based film-profile engineering scheme for fabricating bottom- and double-gated indium-gallium-zinc oxide TFTs
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作者:
Liu, Ping-Che
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Natl Yang Ming Chiao Tung Univ, Inst Elect, 1001 Ta Hsueh Rd, Hsinchu 300, TaiwanNatl Yang Ming Chiao Tung Univ, Inst Elect, 1001 Ta Hsueh Rd, Hsinchu 300, Taiwan
Liu, Ping-Che
[1
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Lin, Po-Jung
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Natl Yang Ming Chiao Tung Univ, Inst Elect, 1001 Ta Hsueh Rd, Hsinchu 300, TaiwanNatl Yang Ming Chiao Tung Univ, Inst Elect, 1001 Ta Hsueh Rd, Hsinchu 300, Taiwan
Lin, Po-Jung
[1
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Chen, Yu-Chi
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Natl Yang Ming Chiao Tung Univ, Inst Elect, 1001 Ta Hsueh Rd, Hsinchu 300, TaiwanNatl Yang Ming Chiao Tung Univ, Inst Elect, 1001 Ta Hsueh Rd, Hsinchu 300, Taiwan
Chen, Yu-Chi
[1
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Chen, Chien-Wei
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Taiwan Instrument Res Inst TIRI, Natl Appl Res Labs, Hsinchu 300, TaiwanNatl Yang Ming Chiao Tung Univ, Inst Elect, 1001 Ta Hsueh Rd, Hsinchu 300, Taiwan
Chen, Chien-Wei
[2
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Kei, Chi-Chung
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Taiwan Instrument Res Inst TIRI, Natl Appl Res Labs, Hsinchu 300, TaiwanNatl Yang Ming Chiao Tung Univ, Inst Elect, 1001 Ta Hsueh Rd, Hsinchu 300, Taiwan
Kei, Chi-Chung
[2
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Li, Pei-Wen
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Natl Yang Ming Chiao Tung Univ, Inst Elect, 1001 Ta Hsueh Rd, Hsinchu 300, TaiwanNatl Yang Ming Chiao Tung Univ, Inst Elect, 1001 Ta Hsueh Rd, Hsinchu 300, Taiwan
Li, Pei-Wen
[1
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Lin, Horng-Chih
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Natl Yang Ming Chiao Tung Univ, Inst Elect, 1001 Ta Hsueh Rd, Hsinchu 300, TaiwanNatl Yang Ming Chiao Tung Univ, Inst Elect, 1001 Ta Hsueh Rd, Hsinchu 300, Taiwan
Lin, Horng-Chih
[1
]
机构:
[1] Natl Yang Ming Chiao Tung Univ, Inst Elect, 1001 Ta Hsueh Rd, Hsinchu 300, Taiwan
[2] Taiwan Instrument Res Inst TIRI, Natl Appl Res Labs, Hsinchu 300, Taiwan
We proposed a novel low-temperature (<110 degrees C) process scheme based on the film-profile engineering technique for fabricating indium-gallium-zinc oxide thin-film transistors (TFTs) with both bottom-gated (BG) and double-gated (DG) configurations. An organic photoresist (PR) suspended bridge is constructed to shadow the depositing species during the deposition processes of the bottom gate-oxide, channel, and source/drain metal films. An Al2O3 layer deposited at 110 degrees C using atomic-layer deposition is employed as the bottom gate-oxide layer. Such a low-temperature process allows us to deposit the Al2O3 layer following the formation of the PR suspended bridge, preventing the formation of organic residues between the gate-oxide and channel layers. As a result, excellent device performance in terms of field-effect mobility of 12.1 cm(2) V-1 s(-1) and subthreshold swing of 141 mV/dec is achieved. Our proposed low-temperature process scheme is readily applicable for fabricating DG TFTs which show substantial enhancements in driving currents.