Critical Threshold Limit for Effective Solder Void Size Reduction by Vacuum Reflow Process for Power Electronics Packaging

被引:1
作者
Yeo, Siang Miang [1 ,2 ]
Yow, Ho-Kwang [2 ,3 ]
Yeoh, Keat Hoe [2 ,3 ]
机构
[1] Amkor Technol Inc, Kuala Langat 42507, Selangor, Malaysia
[2] Univ Tunku Abdul Rahman, Lee Kong Chian Fac Engn & Sci, Dept Elect & Elect Engn, Petaling Jaya 46200, Selangor, Malaysia
[3] Univ Tunku Abdul Rahman, Ctr Photon & Adv Mat Res, Petaling Jaya 46200, Selangor, Malaysia
来源
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2023年 / 13卷 / 07期
关键词
Full factorial design of experiment (DOE); packaging assembly; power MOSFET; solder void; vacuum reflow; voidless; DIE-ATTACH; RELIABILITY;
D O I
10.1109/TCPMT.2023.3293114
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
In recent years, power electronics packaging industry has tightened the tolerance criteria for acceptable solder void size to below 5% in the power packages. Vacuum reflow technology has been introduced to reduce the solder void size in applications, where there is a large contact area coupled with low bond line thickness (BLT). Three critical vacuum reflow parameters which are the pressure level, the pressure pump-down rate, and the vacuum dwell time were studied by using the full-factorial design of the experimental method. The pressure level is shown to be the dominant significance factor, followed by the pressure pump-down rate to a much lesser extent, whereas the vacuum dwell time has minimal effects. The critical threshold of the pressure level required to ensure the achievement of 100% yield in meeting the 5% criteria is estimated to be 8 kPa. Effective solder void size reduction has been consistently demonstrated for a range of solder alloys from high lead Pb95Sn5, eutectic PbSn, to lead-free BiSnAg by using nonclean and low residue flux in post reflow as part of solder paste selection.
引用
收藏
页码:1058 / 1063
页数:6
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