Investigation of the Parasitic Inductance Influence on the Short-Circuit Behaviour of High Voltage IGBTs

被引:3
作者
Du, He [1 ]
Omura, Ichiro [1 ]
Matsumoto, Shuhei [2 ]
Arai, Takuro [2 ]
机构
[1] Kyushu Inst Technol, Next Generat Power Elect Res Ctr, Kitakyushu, Fukuoka, Japan
[2] Toshiba Infrastruct Syst & Solut Corp, Infrastruct Syst Res & Dev Ctr, Tokyo, Japan
来源
2023 IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, APEC | 2023年
关键词
IGBT; short circuit; reliability; parasitic inductance; TCAD simulation;
D O I
10.1109/APEC43580.2023.10131377
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper comprehensively investigates the high voltage insulated-gate bipolar transistor (IGBT) under short-circuit conditions, focusing on the impact of parasitic inductance. At first, the typical short-circuit performance of a 4.5 kV IGBT at different bias voltages is presented and the high equivalent parasitic inductance for the single-chip test is highlighted. Then, an appropriate bias voltage and fixed pulse time are selected as the test condition and the short circuit tests are performed with different values of parasitic inductance. The results show different gate-emitter voltage waveforms and short-circuit time durations. For comparison, the short-circuit test results of a 1.2 kV IGBT with different parasitic inductances are also included, which show consistent gate and current behaviour. A detailed analysis based on the TCAD simulation is included to explain this phenomenon.
引用
收藏
页码:2451 / 2455
页数:5
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